A 16-bit synchronous binary up-counter is clocked with a frequency . f_dk The two most significant bits are ORed together to form an output Y. Measurements shows that Y is periodic and the duration for which Y the remains high in each period is 24 ms. The clock frequency  f_dk is ______ MHz. (Round off to 2 decimal places)

The correct answer is 2.05.

Let us analyze the behavior of the 16-bit synchronous binary up-counter step-by-step.

A 16-bit counter has a total of
$N=2^{16}=65536$
distinct states, ranging from 0 to 65535 (represented in binary from $0000000000000000$ to $1111111111111111$).

Let the bits of the counter be denoted as $Q_{15}{Q}_{14}{Q}_{13}...Q_0$, where $Q_{15}$ and $Q_{14}$ are the two most significant bits (MSBs). The output Y is the logical OR of these two bits:
$Y=Q_{15}OR{Q}_{14}$

During one complete cycle of the counter, the state space can be divided into four equal intervals based on the values of the two MSBs:
1. For the first $2^{14}$ states: $Q_{15}{Q}_{14}=00$, so $Y=0$.
2. For the next $2^{14}$ states: $Q_{15}{Q}_{14}=01$, so $Y=1$.
3. For the next $2^{14}$ states: $Q_{15}{Q}_{14}=10$, so $Y=1$.
4. For the final $2^{14}$ states: $Q_{15}{Q}_{14}=11$, so $Y=1$.

Therefore, the output Y remains high (logic 1) for 3 out of the 4 intervals in each full counter period. The total number of clock cycles for which Y remains high in one period is:

Let $T_{\mathrm{clk}}$ be the period of the clock signal, where $T_{\mathrm{clk}}=1/f_{\mathrm{clk}}$. The duration for which Y remains high is given as 24 ms:
$T_{\mathrm{high}}=N_{\mathrm{high}}\times T_{\mathrm{clk}}=24ms$

Substitute the values to solve for the clock frequency $f_{\mathrm{clk}}$:
$24\times {10}^{-3}s=\frac{49152}{f_{\mathrm{clk}}}$

Rearranging the equation:
$f_{\mathrm{clk}}=\frac{49152}{24\times {10}^{-3}}=2,048,000Hz=2.048MHz$

Rounding off the clock frequency to 2 decimal places gives:
$f_{\mathrm{clk}}\approx 2.05MHz$