Consider TLB, cache and MMU with paging. Which is never be true?

The correct options that can never be true are:

1. TLB miss, PT miss, cache hit
2. TLB hit, PT miss, cache hit

Let us analyze how the Translation Lookaside Buffer (TLB), Page Table (PT), and Cache interact during a virtual memory access to understand why these scenarios are impossible.

1. Understanding the Components:
- TLB (Translation Lookaside Buffer): A fast hardware cache that stores recent virtual-to-physical address translations. A TLB hit means the translation is found immediately.
- PT (Page Table): A data structure in main memory mapping virtual addresses to physical addresses. A PT hit means the page is present in physical memory; a PT miss (page fault) means the page is not in main memory and must be fetched from secondary storage (disk).
- Cache: A high-speed memory that stores blocks of data from physical memory. A cache hit is only possible if the data is already loaded in physical memory.

2. Analyzing Scenario 1: TLB miss, PT miss, cache hit
A PT miss indicates that the requested page is not present in the physical main memory (a page fault has occurred). Since the data does not exist in main memory, it cannot possibly reside in the CPU cache, which only caches data that is currently in main memory. Therefore, a page table miss must always result in a cache miss. A cache hit is impossible during a page table miss. Thus, TLB miss, PT miss, cache hit can never be true.

3. Analyzing Scenario 2: TLB hit, PT miss, cache hit
A TLB hit means that a valid virtual-to-physical address translation exists in the TLB. Because the TLB only caches valid translations for pages that are currently resident in main memory, a TLB hit implies a page table hit (PT hit). It is logically contradictory to have a TLB hit and a PT miss at the same time. Since a PT miss cannot occur alongside a TLB hit, the combination TLB hit, PT miss, cache hit can never be true.